FIG. 11 is a circuit diagram showing a conventional switching power supply device.
This switching power supply device has a power factor improvement circuit provided at the output side of a full-wave rectifying circuit 2 connected to an alternating-current power supply 1, and a DC/DC converting circuit provided at the output side of the power factor improvement circuit. As the switching power supply device being provided with the power factor improvement circuit, the capacitance of an input electrolysis capacitor of the DC/DC converting circuit can be small-sized.
The power factor improvement circuit comprises a coil 3, an N-channel MOSFET (hereinafter referred to as NMOS) 4, a diode 5, a capacitor 6, and a PFC section control circuit 7.
In the power factor improvement circuit, the NMOS 4 is switched on or off in accordance with a control signal output from the PFC section control circuit 7 thereby repeatedly flowing a switching current through the coil 3. The switching current is in proportion to the instant value of a pulsating voltage generated by the full-wave rectifying circuit 2. The coil 3 stores energy therein by letting the switching current flow therethrough, and the stored energy is changed into a direct-current voltage through the diode 5 and charged into the capacitor 6.
The DC/DC converting circuit comprises a transformer 8, an NMOS 9, a diode 10, a capacitor 11, a DC/DC section control circuit 12, and an output voltage detection circuit 13.
The DC/DC section control circuit 12 is a circuit that controls switching on or off of the NMOS 9, and the output terminal of the DC/DC section control circuit 12 is connected to the gate of the NMOS 9. The output voltage detection circuit 13 is a circuit that detects the voltage charged in the capacitor 111 and supplies it to the DC/DC section control circuit 12.
This switching power supply device is further equipped with a load state detection circuit 14 and a PFC on/off switching circuit 15. The load state detection circuit 14 is connected to the DC/DC section control circuit 12. The PFC on/off switching circuit 15 is disposed between the load state detection circuit 14 and the PFC section control circuit 7 of the power factor improvement circuit. The PFC on/off switching circuit 15 actuates or stops the PFC section control circuit 7.
In this switching power supply device, the NMOS 4 is switched on or off in accordance with a control signal generated by the PFC section control circuit 7. When the NMOS 4 is switched on, a switching current flows through the coil 3 and stores energy therein. In a time period in which the NMOS 4 is switched off, the stored energy is supplied to the capacitor 6 via the diode 5 thereby charging the capacitor 6. The capacitor 6 is charged with a voltage E0 which is higher than the alternating-current voltage generated by the alternating-current power supply 1.
On the other hand, the NMOS 9 is switched on or off in accordance with a control signal supplied from the DC/DC section control circuit 12 to the gate of the NMOS 9. When the NMOS 9 is switched on, a switching current flows from the capacitor 6 to a primary winding 8a of the transformer 8 and stores energy therein. When the NMOS 9 is switched off, the stored energy is charged into the capacitor 11 via the diode 10. The capacitor 11 is charged with a direct-current voltage V0 to be supplied to a load 16.
The output voltage detection circuit 13 detects the level of the direct-current voltage V0, and supplies a voltage signal indicating the level of the direct-current voltage V0 to the DC/DC section control circuit 12. The DC/DC section control circuit 12 generates a control signal for setting the timing at which the NMOS 9 is switched on or off based on the voltage signal supplied from the output voltage detection circuit 13. The NMOS 9 is switched on or off in accordance with this control signal. The load state detection circuit 14 outputs a detection result indicating whether the loaded state of the load 16 is lightly loaded or heavily loaded, based on the duty ratio of this control signal.
When the detection result indicates a heavily loaded state, the PFC on/off switching circuit 15 controls the PFC section control circuit 7 to generate a control signal, so that the switching operation will be continued and the resultant energy will be charged into the capacitor 6.
To the contrary, when the detection result indicates a lightly loaded state, the PFC on/off switching circuit 15 controls the control signal from the PFC section control circuit 7 to be fixed at a low level (“L”) so that the switching operation will be stopped. Due to this, the energy generated by the switching current ceases to be charged into the capacitor 6. When the operation of the power factor improvement circuit stops, the power to be consumed drops accordingly. In this state, the DC/DC converting circuit only operates.
As known from the above, a switching power supply device mounted with a conventional power factor improvement circuit includes a device for stopping the operation of the power factor improvement circuit based on the state of the load (see, for example, Unexamined Japanese Patent Application KOKAI Publication No. H8-111975).
As described above, since a conventional switching power supply device has its power factor improvement circuit stop operating when the load 16 is light, it can realize low power consumption. However, since a predetermined startup time is required, after the power factor improvement circuit starts operating, for the output voltage from the power factor improvement circuit to reach a predetermined voltage, trouble is caused if the lightly loaded state and the heavily loaded state are repeated alternately. The trouble will now be explained with reference to FIG. 12.
FIG. 12 is a timing chart for explaining the problem of a conventional switching power supply device.
If the electricity requirements of the load 16 are large and the load 16 is heavy, a load current I0 that flows through the load 16 increases. If the electricity requirements of the load 16 are small and the load 16 is light, the load current I0 flowing through the load 16 decreases and the voltage V0 charged in the capacitor 11 fluctuates. The DC/DC section control circuit 12 generates such a control signal as to make the voltage detected by the output voltage detection circuit 13 constant, thereby setting the timing at which the NMOS 9 is switched on or off.
For example, if the load 16 decreases to under a predetermined value at a time t1, the duty ratio of the control signal is changed. The load state detection circuit 14 detects the state of the load 16 from the duty ratio, and generates, for example, a signal S14 having a low level (hereinafter referred to as “L”) in a time period in which the load 16 is light. In the time period in which the signal S14 of “L” is generated, the control signal to be supplied from the PFC section control circuit 7 to the NMOS 4 is controlled at “L” by the PFC on/off switching circuit 15 thereby the power factor improvement circuit is stopped. In other words, the switching of the NMOS 4 is stopped.
As the power factor improvement circuit being stopped, the voltage E0 charged in the capacitor 6 lowers. If the power factor improvement circuit remains stopped, the charging voltage E0 of the capacitor 6 becomes almost the effective value E1 of the pulsating voltage generated by the full-wave rectifying circuit 2.
Even when the load 16 gets heavy again at a time t2 and the power factor improvement circuit starts operating, a predetermined startup time is required before the output voltage of the power factor improvement circuit reaches a predetermined voltage. Since during this time the load of the switching power supply device is heavy, the charging voltage E0 of the capacitor 6 sharply decreases from the time t2. Afterwards, the charging voltage E0 moderately increases from the time t3.
If the load 16 again becomes light at the time t4 before the charging voltage E0 of the capacitor 6 increases to the full, the operation of the power factor improvement circuit stops and the charging voltage E0 of the capacitor 6 starts decreasing from this time.
As described above, if the state where the load 16 is light and the state where it is heavy appear alternately, there occur time periods t12 to t13, t15 to t16, and t17 to t18 during which the charging voltage E0 of the capacitor 6 largely decreases. Assuming a voltage value E2 [V] as the minimum voltage required for the DC/DC converting circuit to maintain its output voltage V0 constant, the charging voltage E0 of the capacitor 6 falls below the charging voltage value E2 [V] in the time periods t12 to t13, t15 to t16, and t17 to t18, and the output voltage of the DC/DC converting circuit therefore lowers (dips).